This invention relates to an emitter coupled logic (herein referred to as ECL) output circuit.
FIG. 2 shows a prior art inverter circuit using an ECL circuit of this kind, formed with a current switch circuit comprising a pair of transistors Q21 and Q22 (herein referred to as an emitter differential pair 22) and an emitter follower output circuit comprising an output transistor Q23. The base of the transistor Q21 serves as an input terminal 26 where input voltage V.sub.IN is applied, and its collector is connected to a load resistor 21 of resistance R.sub.1. A reference voltage V.sub.REF is applied through a reference voltage source 24 to the base of the transistor Q22. The collector of the transistor Q23 and the load resistor 21 are connected together to a voltage source terminal 27 at potential V.sub.CC. A resistor 25 with resistance R.sub.2 is connected to the emitter of the output transistor Q23, their joint serving as an output terminal 28 where output voltage V.sub.OUT is obtained. The emitters of the transistors Q21 and Q22 are connected together to a grounding terminal 29 (at voltage V.sub.EE) through a constant current source 23 for providing a constant current I.sub.1.
Logic output from the inverter circuit described above will be explained next.
When the input voltage V.sub.IN applied to the input terminal 26 is lower than the reference voltage V.sub.REF (or V.sub.IN &lt;V.sub.REF), a constant current I.sub.1 flows through the transistor Q22, but not through the load resistor 21. Thus, the output V.sub.OUT1 at the output terminal 28 in this situation is given by: EQU V.sub.OUT1 =V.sub.CC -V.sub.BEQ23 ( 1)
where V.sub.BEQ23 denote the voltage between the base and the emitter of the output transistor Q23. When the input voltage V.sub.IN is equal to the reference voltage V.sub.REF (or V.sub.IN =V.sub.REF), the constant current I.sub.1 flows equally (one half each) through the transistors Q22 and Q23. Thus, the output voltage V.sub.OUT2 at the output terminal in this situation is given by: EQU V.sub.OUT2 =V.sub.CC -R.sub.1 I.sub.1 /2-V.sub.BEQ23 ( 2)
When the input voltage V.sub.IN is greater than the reference voltage V.sub.REF (or V.sub.IN &gt;V.sub.REF), the constant current I.sub.1 flows through the load resistor 21, but not through the transistor 23. Thus, the output voltage V.sub.OUT3 in this situation is given by: EQU V.sub.OUT3 =V.sub.CC -R.sub.1 I.sub.1 -V.sub.BEQ23 ( 3)
From (1), (2) and (3) given above, the logic amplitude of the inverter circuit shown in FIG. 2 is obtained as follows: EQU V.sub.OUT1 -V.sub.OUT3 =R.sub.1 I.sub.1 ( 4)
This, however, is subject to the condition R.sub.1 I.sub.1 &lt;2 V.sub.BEQ21 where V.sub.BEQ21 is the voltage between the base and the emitter of the transistor Q21, if the saturation condition of the transistor Q21 is taken into consideration.
The threshold level V.sub.TH0 is given by: EQU V.sub.TH0 =V.sub.REF =V.sub.OUT2 =V.sub.CC -R.sub.1 I.sub.1 /2-V.sub.BEQ23( 5)
This means that the threshold level V.sub.TH0 of the logic output in the case of an inverter circuit using a prior art ECL circuit depends on the voltage V.sub.CC at the voltage source terminal 27 and hence the circuit must be designed with reference to V.sub.CC. In order to stabilize the logic operation, however, V.sub.CC must be stable, and it was necessary to provide V.sub.CC as the ground (GND) potential. This means that a negative voltage V.sub.EE must be applied to the grounding terminal 29, but this makes the interfacing difficult with other circuits driven by a positive voltage.
Moreover, since the logic amplitude given by (4) is subject to the condition R.sub.1 I.sub.1 &lt;2 V.sub.BEQ21, the logic amplitude cannot be designed sufficiently freely, and it was necessary to take noise margin into consideration.